`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:49:54 09/30/2012
// Design Name:   main
// Module Name:   C:/Users/maye/Desktop/carpetas/lab3/test_con_sram.v
// Project Name:  lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: main
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_con_sram;

	// Inputs
	reg [3:0] sel_dato_i;
	reg clk_i;
	reg rst_i;

	// Outputs
	wire [3:0] busleds_o;
	wire [4:0] bcd_o;

	// Instantiate the Unit Under Test (UUT)
	main uut (
		.sel_dato_i(sel_dato_i), 
		.clk_i(clk_i), 
		.rst_i(rst_i), 
		.busleds_o(busleds_o), 
		.bcd_o(bcd_o)
	);
	
	always begin 
		#50 clk_i=~clk_i;
	end
	
	initial begin
		// Initialize Inputs
		sel_dato_i = 8;
		clk_i = 0;
		rst_i = 1;

		// Wait 100 ns for global reset to finish
		#1000;
      rst_i=0;
		// Add stimulus here

	end
      
endmodule

